Grigory Fedyukovich

Since 2016, I am a postdoc at the CSE department of University of Washington, USA, working with Prof. Rastislav Bodik. I completed my PhD at Formal Verification Lab of University of Lugano, Switzerland, under supervision of Prof. Natasha Sharygina.

The main focus of my research is Horn-based Symbolic Model Checking, Automatic Parallelization, Synthesis from Skolemized Proofs of Realizability, Interpolation-based Incremental Verification, and Inductive Simulation Synthesis for Property Directed Program Equivalence. Browse the list of publications in DBLP and check out full texts in ResearchGate.

I sub-reviewed submissions at CAV '17, TACAS '17, FM '16, FMCAD '16, VSTTE '16 (including selected journal submissions), CAV '16, HCVS '16, TACAS '16 (including selected journal submissions), FMCAD '15, CAV '15, FM '15, NFM '15, TACAS '15, JAR-Interpolation '14, CAV '14, PSI '14, FMCAD '14, TACAS '14, FMCAD '13, TACAS '13, VSSE '13, DATE '12, FMCAD '12, GandALF '12, CAV '12, VSTTE '12, FMCAD '11, MEMOCODE '11 and TACAS '11. I was the program chair of VSSE '16 and helped organizing VSSE '14, CAV '13, FMCAD '10 and AVM '10.

I will serve as a local organization chair and a program committee member at the International Conference on Runtime Verification (Seattle, USA, Sept. 12-16 2017). Consider submitting your papers there.

Get more details (including contact details) in my CV.

Last update: February 2017