Prototyping architectures is a non-trivial endeavor. Significant investment in time and dollars is required. This half-day workshop is intended as a forum for the builders in our community to share their practical on-the-ground experiences, to provide a status update on their progress, and to convey insights for those considering prototyping their ideas. Talks that address the following subjects are encouraged:

• Practical guidance on what works & what doesn't, including strategies for:
  • Specification
  • Implementation
  • Verification
  • Physical design issues
• How to balance the often conflicting goals of prototypes being research vehicles and high-performance machines.
• Trade-offs in implementation technologies (FPGAs, ASICs, full-custom).
• How to balance student's thesis goals versus prototype engineering work.
• How to go about funding a prototype.
• Status updates on current prototyping efforts.

Contributions are encouraged from all members of the architecture community, including those considering embarking on a prototyping effort (as well as those who strongly disagree with the need to build prototypes). Submitted abstracts do not need to necessarily address the points above, but may instead simply discuss the prototype and provide a brief update on its current status. The organizers of the workshop will be in contact with the submission authors to follow up on what sort of content they would be interested in presenting.

Organizers: Mark Oskin & Doug Burger

Submission instructions:

• Deadline: April 21st, 2006
• Submission process: PDF formatted documents emailed to oskin@cs.washington.edu
• Submission guidelines: Two-page extended abstracts with reasonable fonts & spacing. You may include an appendix of any length but we will not promise to read it. The purpose of this appendix is to include things such as pictures of your prototype, tables, figures, or other items that help clarify the 2 page abstract.
• Extensions of the deadline will not be granted. Early submissions will happily be accepted, however.

The authors of accepted abstracts will be asked to give a brief talk at the workshop. There will be no formal proceedings, however, slides will be posted on the web (i.e. HotChips style).

Brief Program schedule: (Sunday morning)

• 8:30 - Steve Keckler, Designing a Large Scale Custom Prototype Chip: the Good, the Bad, and the Ugly
• 9:00 - Mike Taylor, RAW retrospective
• 9:20 - Karu Sankaralingam, The TRIPS System-level Design
• 9:40 - Andrew Putnam, The WaveScalar prototype system
• 10:00 - Krste Asonvic, RAMP: Research Accelerator for Multiprocessors

• 10:30 - Break

• 11:00 - Jack Dennis, Prototyping a Fresh Breeze System
• 11:20 - Javi Martinez, SCOORE: Santa Cruz Out-of-Order Risk Engine, FPGA Design Issues
• 11:40 - Myles Watson, Designing Large Memories Using Hardware Prototyping
• 12:00 - Smruti Srangi, Rapid Prototyping in Architecture Research using Existing Hardware Mechanisms
• 12:20 - 10 min conclude

Full Program (with abstracts)

• 8:30 - Steve Keckler, Designing a Large Scale Custom Prototype Chip: the Good, the Bad, and the Ugly
  Because implementing large-scale custom processors is typically done for commercial purposes, there is usually a dearth of information about the details of the design. The purpose of this talk is to lift the lid on the design and implementation of the 170 million transistor TRIPS processor chip completed using a 130nm ASIC process. While a running theme of the talk will be how the tiled nature of the architecture simplified the design process, I will provide details on what aspects of our methodology worked well and where we were forced to scale back our expectations. I will also discuss the lessons learned during the design and implementation process and make recommendations on how to go about prototyping future designs in custom ASIC chips.
• 9:00 - Mike Taylor, RAW retrospective
• 9:20 - Karu Sankaralingam, The TRIPS System-level Design
  
• 9:40 - Andrew Putnam, The WaveScalar prototype system
• 10:00 - Krste Asonvic, RAMP: Research Accelerator for Multiprocessors

• 10:30 - Break

• 11:00 - Jack Dennis, Prototyping a Fresh Breeze System
  The Fresh Breeze Project addresses the programmability of multi-core processing chips through novel architecture and support for an extended functional programming paradigm. The processor cores are of simultaneous multithreading design with multiple instruction issue per cycle. Four threads are provided per core, and it is anticipated that one Fresh Breeze chip might contain eight or more cores. A novel memory model is employed in which 1024-bit memory chunks having 64-bit unique identifiers are created, initialized, shared among threads, and released to a free storage pool when they become inaccessible. Once initialized, a chunk is never updated. The presetation will cover the approach adopted for testing and evaluating the architecture, and plans for building a prototype sytem using FPGA technooogy. Software issues including strategy for building a cycle-accurate simulator, a scheme for compiling user code for the simulator and prototype, and plans for bootstrapping operating software will also be discussed.
• 11:20 - Francisco J. Mesa-Martinez, SCOORE: Santa Cruz Out-of-Order Risk Engine, FPGA Design Issues
  Authors: Francisco Javi Mesa-Martinez, Suraj Narender Kurapati, Melisa Nunez, Abhishek Sharma, Keertika Singh, Joseph Nayfach, Sean Halle, Carlos Andres Cabrera, Sangeetha Nair, Hari Kolakaleti, Jose Renau
  Continuous improvements on FPGA technology are changing the semiconductor industry. Many companies provide simple in-order processors synthesizable on FPGAs. Currently, only single issue in-order processors are available as soft-cores for FPGAs. The reason is that complex out-of-order processor or even in-order superscalar processors do not map well to FPGA designs. While single issue and superscalars tend to have similar frequency targets on ASIC, there can be one order of magnitude difference for FPGAs. As a result, for FPGAs, a simple in-order processor is faster and more efficient that superscalar one. At Santa Cruz, we are developing an out-of-order 4-way superscalar processor with good performance mappings on FPGAs and ASIC. The project is called SCOORE, and it stands for Santa Cruz Out-of-Order Risk Engine. SCOORE is a SPARC V8 compatible processor with a target frequency of 125MHz with an Altera Stratix II, and 900MHz with 90nm ASIC.
• 11:40 - Myles Watson, Designing Large Memories Using Hardware Prototyping
  This talk discusses the use of an off-the-shelf FPGA board as a prototyping vehicle for memory design. When the prototype is mapped into the physical address space of a system, it can see and respond to each cache miss. Researchers can then focus on the memory accesses of the machine, without having to model the complexities of out-of-order microprocessors, buses, other hardware, and their interactions.
• 12:00 - Smruti Srangi, Rapid Prototyping in Architecture Research using Existing Hardware Mechanisms
  We try to make the case for using lesser known features in COTS(Commodity off the shelf) processors to prototype architectural research ideas. We survey a set of features in Intel processors and chipsets that can help us implement or estimate the overheads of advanced architectural enhancements. We show that these features have diverse uses in performance evaluation, power management, reliability, and support for programming languages.
• 12:20 - 10 min conclude