CSE 378: Machine Organization and Assembly Language

Purpose:

Fundamentals of instruction set design. CPU implementation, pipelining. Memory hierarchy. Assembly language programming. Compiler and Operating System interfaces.

Precondition concepts:

• basics of computation
• abstraction
  • modularity, encapsulation
  • interface vs. implementation
• basic Boolean logic
• simple abstract data types (stacks, queues) and their implementations

Precondition Abilities:

• design and implement medium-sized programs (up to about 1000 lines), consisting of several (4-12) modules
• understand and extend medium-sized (500+ lines) programs
• read, write, use, and document (own and others') software components
• write clients, implementations separately, given spec of interface

Precondition Skills:

• programming skill in C and/or C++

Post condition concepts:

• basic computer organization
  • CPU, memory, I/O
  • representation of integers in various bases (binary, octal, hexadecimal)
• performance metrics for computer systems
  • execution time, CPI
  • MIPS, MFLOPS
• instruction set design
  • registers
  • arithmetic-logical instructions
  • load-store instructions and operand addressing
  • flow of control instructions
• instruction encoding
  • instruction formats
  • RISC vs. CISC
• interface with the compiler
  • user stack
  • procedure call conventions
• basic processor implementation
  • functional behavior of basic building blocks
  • simple data path
  • multiple cycle implementation
  • simple control unit
• pipelining
  • ideal pipeline
  • data hazards & forwarding
  • control hazards & branch prediction
• instruction-level parallelism
• memory hierarchy
• caches
  • cache organizations
  • performance metrics for caches, taxonomy of cache misses
  • parameters for cache design
  • write strategies
• memory management
  • virtual memory; paging
  • virtual memory translation, page tables
  • TLB's
• busing structures
• input-output
  • devices
  • interrupts (interaction with operating system)

Postcondition Abilities:

• design at the black box level a simple pipelined CPU
• design and simulate varied cache and TLB organizations
• understand the underlying metrics for the performance of a single processor computer system

Postcondition Skills

• program and debug assembly language routines for a simple RISC ISA (MIPS 2000/3000)
• basic knowledge of microarchitecture and memory hierarchy simulation
• familiarity with creating, manipulating, and editing files within the framework of a multi-user timesharing system.