A 5.5GHz Fractional Frequency-Synthesizer IC

Presented 10/15/97 at the 1997 IEEE GaAs IC Symposium in Anaheim, CA

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Table of Contents

A 5.5GHz Fractional Frequency-Synthesizer IC  
Phase-Locked Loops 
PLL Design Tradeoffs 
The Design Goals 
GaAs/AlGaAs HBTs 
The GaAs/AlGaAs Process 
The FSP-5 IC 
A High-Performance Loop Application 
FSP-5 Speed and Phase Noise 
Gain Variation and Normalizer Linearity 
Future Directions
Author: C. Diorio 

Email: diorio@cs.washington.edu 

Home Page: http://www.cs.washington.edu/people/faculty/diorio/