Relevance of Hierarchical Memory Model

Level Amount Speed

Registers Up to 64 words 1 Clock cycle

L1 cache(On chip) 8Kb to 32Kb 1-2 clock cycles

(But pipelined)

L2 cache(off chip) 512Kb to 2048 Kb ᡂ clock cycles

(Static RAM)

Main memory 32Mb to 4Gb  clock cycles

(Dynamic RAM)

Disk Gb’s to Tb’s � clock cycles

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