In collaboration with researchers at DEC Systems Research Center, we developed techniques to allow us to build a prototype switch for an arbitrary topology point-to-point network with link speeds of up to one gigabit per second. The switch deals in fixed-length ATM-style cells, which it can process at a rate of 37 million cells per second. It provides high bandwidth and low latency for datagram traffic. In addition, it supports real-time traffic by providing bandwidth reservations with guaranteed latency bounds. The key to the switch's operation is a novel technique called parallel iterative matching, which can quickly identify a set of conflict-free cells for transmission in a time slot. Bandwidth reservations are accommodated in the switch by building a fixed schedule for transporting cells from reserved flows across the switch; we show that we can provide performance guarantees even when the switches and hosts operate with unsynchronized clocks. Parallel iterative matching can fill unused slots with datagram traffic. Finally, we note that parallel iterative matching may not allocate bandwidth fairly among flows of datagram traffic. We present a technique called statistical matching, which can be used to ensure fairness at the switch and to support applications with rapidly changing needs for guaranteed bandwidth. The ideas developed in this work have formed the basis of the next generation of DEC's networking products. More recently, we have examined scheduling algorithms as alternatives to parallel iterative matching, to reduce the hardware complexity of switch scheduling without sacrificing switch throughput.