Luis Vega

PhD student
Computer Science
University of Washington
CSE 314
vegaluis@cs.washington.edu
[CV]

About me

I’m a first year PhD student in Computer Science at the Paul G. Allen School. I’m a member of the Sampa group and work with Michael Taylor. My research interests include computer architecture, systems, and networking.

Publications

Conference Papers

Hiding Intermittent Information Leakage with Architectural Support for Blinking.
Alric Althoff, Joseph McMahan, Luis Vega, Scott Davidson, Timothy Sherwood, Michael B. Taylor, and Ryan Kastner.
ISCA, 2018.
[Paper]

Celerity: An Open-Source RISC-V Tiered Accelerator Fabric.
Tutu Ajayi, Khalid Al-Hawaj, Aporva Amarnath, Steve Dai, Scott Davidson, Paul Gao, Gai Liu, Atieh Lotfi, Julian Puscar, Anuj Rao, Austin Rovinski, Loai Salem, Ningxiao Sun, Christopher Torng, Luis Vega, Bandhav Veluri, Xiaoyang Wang, Shaolin Xie, Chun Zhao, Ritchie Zhao, Christopher Batten, Ronald G. Dreslinski, Ian Galton, Rajesh K. Gupta, Patrick P. Mercier, Mani Srivastava, Michael B. Taylor, and Zhiru Zhang.
HOTCHIPS, 2017.
[Slides]

Moonwalk: NRE Optimization in ASIC Clouds.
Moein Khazraee, Lu Zhang, Luis Vega and Michael Bedford Taylor.
ASPLOS, 2017.
[Paper]

ASIC Clouds: Specializing the Datacenter.
Ikuo Magaki, Moein Khazraee, Luis Vega Gutierrez and Michael Bedford Taylor.
ISCA, 2016.
[Paper]

Journal Papers

The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips. Scott Davidson, Shaolin Xie, Christopher Torng, Khalid Al-Hawaj, Austin Rovinski, Tutu Ajayi, Luis Vega, Chun Zhao, Ritchie Zhao, Steve Dai, Aporva Amarnath, Bandhav Veluri, Paul Gao, Anuj Rao, Gai Liu, Rajesh K. Gupta, Zhiru Zhang, Ronald G. Dreslinski, Christopher Batten, and Michael B. Taylor.
IEEE Micro, vol. 38 no. 2, p. 30–41, March-April, 2018.
[Paper]

Specializing a Planet’s Computation: ASIC Clouds.
Moein Khazraee, Luis Vega Gutierrez, Ikuo Magaki and Michael Bedford Taylor.
IEEE MICRO vol. 37 no. 3, p. 62-69, May-June, 2017.
[Paper]

Workshops

RV-IOV: Tethering RISC-V Processors via Scalable I/O Virtualization
Luis Vega and Michael Bedford Taylor.
CARRV, 2017 (colocated with MICRO 2017).
[Paper] [Slides]

Experiences Using the RISC-V Ecosystem to Design an Accelerator-Centric SoC in TSMC 16nm.
Tutu Ajayi, Khalid Al-Hawaj, Aporva Amarnath, Steve Dai, Scott Davidson, Paul Gao, Gai Liu, Anuj Rao, Austin Rovinski, Ningxiao Sun, Christopher Torng, Luis Vega, Bandhav Veluri, Shaolin Xie, Chun Zhao, Ritchie Zhao, Christopher Batten, Ronald G. Dreslinski, Rajesh K. Gupta, Michael B. Taylor, and Zhiru Zhang.
CARRV, 2017 (colocated with MICRO 2017).
[Paper]

RISC-V at UC San Diego.
Pulkit Bhatnagar, Scott Davidson, Anuj Rao, Luis Vega, Shaolin Xie, Chun Zhao, and Michael Bedford Taylor.
5th RISC-V workshop, 2016.
[Slides]

Tech reports

Power Side Channels in Security ICs: Hardware Countermeasures.
Lu Zhang, Luis Vega, and Michael Bedford Taylor.
Technical Report CS2015-12, Department of Computer Science and Engineering, University of California San Diego, 2015.
[Report]