PhD student
Paul G. Allen School of Computer Science & Engineering
University of Washington
vegaluis@cs.washington.edu

About me

I am a second year PhD student in the Paul G. Allen School of Computer Science & Engineering at the University of Washington. I am advised by Luis Ceze and part of the SAMPL group.

I am broadly interested on building, programming, and deploying systems based on hardware accelerators. Although there are two clear benefits of hardware acceleration, including performance and energy efficiency, nowadays the cost, i.e. man-hours, of accelerating applications is really high compared to using conventional computing hardware. My research focuses on reducing this cost via tools and automation.

Publications

A Hardware-Software Blueprint for Flexible Deep Learning Specialization.
Thierry Moreau, Tianqi Chen, Luis Vega, Jared Roesch, Lianmin Zheng, Eddie Yan, Josh Fromm, Ziheng Jiang, Luis Ceze, Carlos Guestrin, Arvind Krishnamurthy.
IEEE Micro, vol. 39, no. 5, pp. 8-16, 1 Sept.-Oct. 2019.

A 1.4 GHz 695 Giga RISC-V Inst/s 496-core Manycore Processor with Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS.
Austin Rovinski, Chun Zhao, Khalid Al-Hawaj, Paul Gao, Shaolin Xie, Christopher Torng, Scott Davidson, Aporva Amarnath, Luis Vega, Bandhav Veluri, Anuj Rao, Tutu Ajayi, Julian Puscar, Steve Dai, Ritchie Zhao, Dustin Richmond, Zhiru Zhang, Ian Galton, Christopher Batten, Michael B. Taylor, and Ron G. Dreslinski.
IEEE Symp. on VLSI Technology and Circuits, June 2019.
[Paper]

Extreme Datacenter Specialization for Planet-Scale Computing: ASIC Clouds.
Shaolin Xie, Scott Davidson, Ikuo Magaki, Moein Khazraee, Luis Vega, Lu Zhang, and Michael B. Taylor.
ACM SIGOPS Operating Systems Review, vol. 52 no. 1, p 96-108, August, 2018.
[Paper]

Hiding Intermittent Information Leakage with Architectural Support for Blinking.
Alric Althoff, Joseph McMahan, Luis Vega, Scott Davidson, Timothy Sherwood, Michael B. Taylor, and Ryan Kastner.
ISCA, 2018.
[Paper]

The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips.
Scott Davidson, Shaolin Xie, Christopher Torng, Khalid Al-Hawaj, Austin Rovinski, Tutu Ajayi, Luis Vega, Chun Zhao, Ritchie Zhao, Steve Dai, Aporva Amarnath, Bandhav Veluri, Paul Gao, Anuj Rao, Gai Liu, Rajesh K. Gupta, Zhiru Zhang, Ronald G. Dreslinski, Christopher Batten, and Michael B. Taylor.
IEEE Micro, vol. 38 no. 2, p. 30–41, March-April, 2018.
[Paper]

RV-IOV: Tethering RISC-V Processors via Scalable I/O Virtualization.
Luis Vega and Michael Bedford Taylor.
CARRV, 2017 (colocated with MICRO 2017).
[Paper]

Experiences Using the RISC-V Ecosystem to Design an Accelerator-Centric SoC in TSMC 16nm.
Tutu Ajayi, Khalid Al-Hawaj, Aporva Amarnath, Steve Dai, Scott Davidson, Paul Gao, Gai Liu, Anuj Rao, Austin Rovinski, Ningxiao Sun, Christopher Torng, Luis Vega, Bandhav Veluri, Shaolin Xie, Chun Zhao, Ritchie Zhao, Christopher Batten, Ronald G. Dreslinski, Rajesh K. Gupta, Michael B. Taylor, and Zhiru Zhang.
CARRV, 2017 (colocated with MICRO 2017).
[Paper]

Celerity: An Open-Source RISC-V Tiered Accelerator Fabric.
Tutu Ajayi, Khalid Al-Hawaj, Aporva Amarnath, Steve Dai, Scott Davidson, Paul Gao, Gai Liu, Atieh Lotfi, Julian Puscar, Anuj Rao, Austin Rovinski, Loai Salem, Ningxiao Sun, Christopher Torng, Luis Vega, Bandhav Veluri, Xiaoyang Wang, Shaolin Xie, Chun Zhao, Ritchie Zhao, Christopher Batten, Ronald G. Dreslinski, Ian Galton, Rajesh K. Gupta, Patrick P. Mercier, Mani Srivastava, Michael B. Taylor, and Zhiru Zhang.
HOTCHIPS, 2017.
[Slides]

Specializing a Planet’s Computation: ASIC Clouds.
Moein Khazraee, Luis Vega Gutierrez, Ikuo Magaki and Michael Bedford Taylor.
IEEE Micro vol. 37 no. 3, p. 62-69, May-June, 2017.
[Paper]

Moonwalk: NRE Optimization in ASIC Clouds.
Moein Khazraee, Lu Zhang, Luis Vega and Michael Bedford Taylor.
ASPLOS, 2017.
[Paper]

ASIC Clouds: Specializing the Datacenter.
Ikuo Magaki, Moein Khazraee, Luis Vega Gutierrez and Michael Bedford Taylor.
ISCA, 2016.
[Paper]

Tech reports

Power Side Channels in Security ICs: Hardware Countermeasures.
Lu Zhang, Luis Vega, and Michael Bedford Taylor.
Technical Report CS2015-12, Department of Computer Science and Engineering, University of California San Diego, 2015.
[Report]