email: wysem at cs dot washington dot edu
News Flash: As of July 2022 I have joined AMD Research full time as a MTS Silicon Design Engineer. I will be finishing my PhD while working at AMD.
I am a Ph.D. student in the Paul G. Allen School of Computer Science & Engineering at the University of Washington. I am a member of the Sampa research group, advised by Prof. Mark Oskin. I also work closely with Prof. Michael Taylor. My research interests are in the field of computer architecture, and my current research focuses on the design and implementation of the open-source BedRock cache coherence protocol and programmable coherence engine in the BlackParrot RISC-V 64-bit multicore processor. In addition, my research interests include GPU architecture, hardware specialization, and computer science education. I greatly enjoy teaching and have been a Teaching Assistant for UW CSE courses at the undergraduate and graduate level, in the Professional Master's Program, and for a massively online open course offering of CSE 351: The Hardware/Software Interface through Coursera. I have also had the pleasure of being the instructor for CSE 351: The Hardware/Software Interface (WI'18, WI'21) and CSE 369: Introduction to Digital Design (SP'22).
I spent all of 2017 on leave from UW CSE, working as a Post-Grad Scholar at AMD Research. My work at AMD focused on GPU architecture and microarchitecture optimizations for accelerating GPGPU applications, specifically optimizing the use of the vector register file in GPGPU architectures (see my quals report). I also contributed to the development of the GCN3 based simulation of GPUs in the gem5 simulator (paper, gem5).
I received my M.S. Computer Science and Engineering and B.S. Computer Engineering from the Dept. of Computer Science & Engineering at the University of Washington in December 2015 and June 2014, respectively.
My (hopefully, but often not, up-to-date) CV can be found here.
My research interests are in the field of computer architecture and revolve around (a) cache coherence, specifically for in-order multicore processors, (b) open-source hardware design, (c) programmability in the memory system, (d) general purpose parallel computing (e.g., GPGPU-styled architectures), and (e) hardware specialization.
My current research is centered around the design and implementation of the cache coherence protocol for the open-source BlackParrot RISC-V multicore processor. I am the lead architect and developer of the cache coherence protocol and its associated programmable and fixed-function coherence engines. The design and implementation of BlackParrot is fully open-source. Accelerating the adoption of open-source hardware requires not only an open ISA, but also open-source implementations that can be easily taken from RTL to tapeout.
Aside from technical research, I am also very interested in computer engineering education and curriculum. As the underlying technology of computing systems changes, how should that change the curriculum we provide and teach? How do we design and teach courses in an equitable, inclusive, and productive (for both learner and teacher) way?
My past research has spanned a variety of topics, including data processing for novel DNA sequencing technology, modeling approximate computing techniques (see REACT), and the evaluation and comparison of a neural network accelerator on reconfigurable hardware using high level synthesis (see SNNAP).