David Kohlbrenner

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Info

I am an Assistant Professor in the Paul G. Allen School of Computer Science and Engineering at the University of Washington.
Previously I was a post-doc with Dawn Song and the ADEPT lab at UC Berkeley, and did my PhD with Hovav Shacham at UC San Diego.

Google Scholar profile

Contact: dkohlbre [at] cs.washington.edu -or- david.kohlbrenner [at] gmail.com

Research

My research interests span software security, systems, and hardware architecture.
I put special focus on the impact of hardware design on high-level software security.

Active projects include:
Next generation microarchitectural side-channels and formal defenses.
FPGA analog side-channels.
The Keystone TEE framework for RISC-V.

Teaching

CSE484 Computer Security and Privacy (Fall 2021, Winter 2021)
CSE564 (Graduate) Computer Security and Privacy (Fall 2020)
CSE599 Hardware Security (Spring 2022)

Previously:
Advanced topics on secure hardware (UC Berkeley)
CSE80 Linux and the Command Line aka T4CS (UC San Diego)

Conference Publications

J. Vicarte, P. Shome, N. Nayak, C. Trippel, A. Morrison, D. Kohlbrenner, C. Fletcher "Opening Pandora's Box: A Systematic Study of New Ways Microarchitecture Can Leak Private Data" ISCA, 2021.
D. Lee, D. Kohlbrenner, S. Shinde, D. Song, K. Asanovic "Keystone: An Open Framework for Architecting TEEs" EuroSys 2020.
I. Lebedev, K. Hogan, J. Drean, D. Kohlbrenner, D. Lee, K. Asanovic, D. Song, S. Devadas "Sanctorum: A lightweight security monitor for secure enclaves" Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2019.
D. Kohlbrenner and H. Shacham "On the effectiveness of mitigations against floating-point timing channels." USENIX Security. August 2017
Tools and attack details
Slides
C. Disselkoen, D. Kohlbrenner, L. Porter, D. Tullsen "Prime+Abort: A Timer-Free High-Precision L3 Cache Attack using Intel TSX" USENIX Security. August 2017
D. Kohlbrenner and H. Shacham "Trusted Browsers for Uncertain Times." USENIX Security. August 2016
Second place at CSAW Applied Research 2016
Slides
M. Andrysco, D. Kohlbrenner, K. Mowery, R. Jhala, S. Lerner, and H. Shacham "On Subnormal Floating Point and Abnormal Timing." IEEE Security and Privacy (Oakland), May 2015 (Updated June 2017, original)
Slides
K. Mowery, M. Wei, D. Kohlbrenner, H. Shacham, and S. Swanson "Welcome to the Entropics: Boot-Time Entropy in Embedded Devices." IEEE Security and Privacy (Oakland), May 2013

Other Publications

G. Andrade, D. Lee, D. Kohlbrenner, K. Asanovic, D. Song "Software-Based Off-Chip Memory Protection for RISC-V Trusted Execution Environments" Workshop on Computer Architecture Research with RISC-V (CARRV), May 2020
K. Cheang, C. Rasmussen, D. Lee, D. Kohlbrenner, K. Asanovic, S. Seshia "Verifying RISC-V Physical Memory Protection" Workshop on Secure RISC-V Architecture Design (SECRISC-V 2020), Aug 2020
D. Kohlbrenner, S. Shinde, D. Lee, K. Asanovic, D. Song "Building Open Trusted Execution Environments" IEEE Security & Privacy Magazine ( Volume: 18 , Issue: 5 , Sept.-Oct. 2020 )