Luis Ceze
Associate Professor
Department of Computer Science and Engineering
Microsoft Research Faculty Fellow
Sloan Foundation Research Fellow
University of Washington
Box 352350
Seattle, WA 98195
Paul G. Allen Center, Room 576
(206) 543-1896 [phone], (206) 616-3804 [fax]
Our research group: sampa.
My official UW CSE webpate.
CSE590G Architecture Seminar (ongoing)
Coursera The Hardware/Software Interface, Spring 2013
CSE351 The Hardware/Software Interface, Spring 2013
CSEP548 Computer Systems Architecture (PMP), Fall 2012
CSE351 The Hardware/Software Interface, Fall 2011
CSE351 The Hardware/Software Interface, Spring 2011
CSEP548 Computer Systems Architecture, Winter 2011
CSE378 Machine Organization & Assembly Language, Spring 2010
CSE548 Computer Systems Architecture, Winter 2010
CSEP548 Computer Systems Architecture (PMP), Spring 2009
CSE378 Machine Organization & Assembly Language, Winter 2009
CSE599Q Topics in Multiprocessor Programmability, Spring 2008
CSE590P Programming Systems Seminar, Winter 2008 (with Dan Grossman)
CSE548 Computer Systems Architecture, Winter 2008
CSE378 Machine Organization & Assembly Language, Fall 2007
Most of my research is in improving programmability and reliability of multiprocessor and multicore systems. It includes innovation in architecture, compilers, programming models and operating systems. I am the lead faculty in the sampa project.
Some recent selected publications (full list):
"DNA-based Molecular Architecture with Spatially Localized Components", ISCA 2013 (to appear).
"Cooperative Empirical Failure Avoidance for Multithreaded Programs", ASPLOS 2013.
"DDOS: Taming Nondeterminism in Distributed Systems", ASPLOS 2013.
"Neural Acceleration for General-Purpose Approximate Programs", MICRO 2012 (Selected as IEEE Micro Top Picks).
"IFRit: Interference-Free Regions for Dynamic Data-Race Detection", OOPSLA 2012.
"RADISH: Always-On Sound and Complete Race Detection in Software and Hardware", ISCA 2012.
"Architectural Support for Disciplined Approximate Programming", ASPLOS 2012.
"On the Impact of Memory Models on Software Reliability in Multiprocessors", PODC 2011.
"EnerJ: Approximate Data Types for Safe and General Low-Power Computation", PLDI 2011.
"Isolating and Understanding Concurrency Errors Using Reconstructed Execution Fragments", PLDI 2011.
"Operating System Implications of Fast, Cheap, Non-Volatile Memory", Usenix HotOS 2011.
"RCDC: A Relaxed Consistency Deterministic Computer", ASPLOS 2011.
"Checked Load: Architectural Support for JavaScript Type-Checking on Mobile Processors Authors", HPCA 2011.
"A Limit Study of JavaScript Parallelism", IISWC 2010.
"Composable Specifications for Structured Shared-Memory Communication", OOPSLA 2010.
"Deterministic Process Groups in dOS", OSDI 2010.
"Conflict Exceptions: Providing Simple Concurrent Language Semantics with Precise Hardware Exceptions", ISCA 2010.
"ColorSafe: Architectural Support for Debugging and Dynamically Avoiding Multi-variable Atomicity Violations", ISCA 2010.
"CoreDet: A Compiler and Runtime System for Deterministic Multithreaded Execution", ASPLOS 2010.
"Finding Concurrency Bugs with Context-Aware Communication Graphs", MICRO 2009.
"The Bulk Multicore Architecture for Improved Programmability", CACM Dec'09.
"The Case for System Support for Concurrency Exceptions", USENIX HotPar 2009.
"DMP: Deterministic Shared Memory Multiprocessing", ASPLOS 2009. Selected for the IEEE Micro Top Picks 2009.
"Atom-Aid: Detecting and Surviving Atomicity Violations", ISCA 2008. Selected for the IEEE Micro Top Picks 2008.
"DeLorean: Recording and Deterministically Replaying Shared-Memory Multiprocessor Execution Efficiently", ISCA 2008. Selected for CACM Research Highlights 2009.
"SoftSig: Software-Exposed Hardware Signatures for Memory Disambiguation", ASPLOS 2008. Selected for the IEEE Micro Top Picks 2008.
"BulkSC: Bulk Enforcement of Sequential Consistency", ISCA 2007.
"Implicit Parallelism with Ordered Transactions", PPoPP 2007.
"Colorama: Architectural Support for Data-Centric Synchronization", HPCA 2007.
"Bulk Disambiguation of Speculative Threads in Multiprocessors ", ISCA 2006.
If you need a good architecture simulator, take a look at SESC, a very fast multiprocessor simulator. And here is a good way of choosing your next architecture or compiler conference.
Take a look at the collectively written white-paper on 21st Century computer architecture research.
I am lucky to have my research supported by Microsoft, Intel, Google, Qualcomm, NSF, and the Pacific Northwest National Laboratory. I am also a member of the Center for Future Architectures Research.
I received an NSF CAREER Award and a Microsoft Research Faculty Fellowship to develop ideas on deterministic multiprocessing and multicore programmability in general.I have the pleasure of working with the following incredible graduate students:
Katelin BaileyAnd postdoc Ben Ransford, who just joined the group!
And these two fantastic students graduating soon and currently applying for academic and industrial jobs:
Hadi EsmaeilzadehIn 2008 I co-founded Corensic(former PetraVM) together with Mark Oskin and Peter Godman to commercialize technology initially developed at UW-CSE.
I was born in São Paulo, Brazil.
I received my PhD in Computer Science from University of Illinois at Urbana-Champaign. I got my BEng and MEng in Electrical Engineering from University of São Paulo, Brazil.
I am very fortunate to have such a happy family.
My (much smarter than me) brother is freezing in Michigan but having fun with aerospace engineering.
I am always happy because she
exists.
